1. Field of the Invention
This invention relates to a non-volatile memory (EEPROM) such as a flash memory that is capable of being electrically rewritten, and in particular to a non-volatile memory that is capable of erasing a plurality of sectors in a short time.
2. Related Art
A flash memory has non-volatile memory cells that have floating gates. A flash memory comprises a plurality of a sectors each of which has a plurality of memory cells, and the memory is erased (deleted) in sector units and programmed (written) for each memory cell.
FIG. 1 is a figure for explaining the erasure operation for a prior non-volatile memory. FIG. 1 shows a cross section of a non-volatile memory cell. This memory cell is formed from an N-type drain 2 and source 3 inside the P-type well area 4 of an N-type silicon semiconductor substrate 1, and comprises a floating gate FG and control gate CG on the channel area. Also, the drain 2 is connected to a bit line BL, and the control gate CG is connected to a word line WL (or jointly used). In addition, the source 3 is connected to a source line SL.
For the memory cell, the erasure state (data 1) is the state when the threshold voltage of the cell transistor is low without electrons entering the floating gate FG, and the program state (data 0) is the state when electrons enter the floating gate FG and the threshold voltage of the cell transistor is high.
In order to erase a memory cell that is in the program state, a negative voltage (for example xe2x88x929V) is applied to the control gate CG from the word line WL, the bit line BL is caused to be open, and a step-up voltage VPS is applied to the source 3 from the source line SL, so that a large pulse voltage is applied in the direction from the source 3 to the floating gate FG and the electrons in the floating gage FG are removed to the source side, or it is also possible to draw electrons to the P-well area 4 by making the P-type well area 4, a channel of cell, the same potential as the source 3. These are called erasure pulse or erasure stress. The step-up voltage VPS is a higher voltage than the power-supply VCC, and is generally generated by a step-up voltage circuit 12 that is provided internally. However, the current-supply capability of this step-up voltage circuit 12 is limited.
The flash memory comprises a plurality of sectors, and the aforementioned erasure operation is performed for each sector. In this case, even in case of erasing a plurality of sectors, the erasure operation is not performed for the plurality of sectors at the same time, but is performed one sector at a time. The reasons for this are, first, when erasing a sector, it is necessary to apply the step-up voltage VPS to all of the cell sources 3 (or channel or well 4) in a sector, however, since the electrons that have built up in the floating gate FG are drawn out to the source, a relatively large current flows to the source 3. However, since the step-up voltage circuit 12 generates a higher step-up voltage by a pumping operation from the power-supply voltage, the current-supply capability is limited as mentioned above. Therefore, it is not possible to apply the step-up voltage VSP simultaneously to all of memory cells in the plural sectors. Second, when an erasure stress is applied to all of the sectors at the same time, there is the problem that some cells will be over erased due to variation in cell characteristics, and the threshold voltage becomes negative. For the over erased cells, self convergence, or recovery process, is performed by a light program operation for returning the threshold voltage to a positive voltage. However, in order to decrease the erasure time, it is necessary to reduce this self-convergence operation as much as possible, and should be avoid when possible.
Recently, with the increase in capacity of flash memory, the number of sectors has increased and the number of processes for erasing more sectors has increased. This has resulted in the problem that the erasure time has become longer.
The objective of this invention is to provide a non-volatile memory that is capable of reducing the erasure processing time when erasing a plurality of sectors.
In order to accomplish the aforementioned objective, a first aspect of the present invention is a flash memory, wherein when erasing a plurality of sectors an erasure process of applying a normal erasure stress to one sector is performed, while at the same time, a pre-erasure process of applying a pre-erasure stress, that is weaker than the normal erasure stress, to the other sectors to be erased is performed. By performing a pre-erasure process to the other sectors while the normal erasure process is being performed, it is possible to shorten the following erasure processing for the other sectors.
In order to accomplish the aforementioned objective, according to a second aspect of the invention, when erasing a plurality of sectors of a flash memory, a normal erasure process of applying a step-up voltage to the cell source or channel is performed, while at the same time, a pre-erasure process of applying a power-supply voltage, that is lower than the step-up voltage applied cell source or channel, to other sectors to be erased is performed.
By performing pre-erasure processing for other sectors to be erased while performing normal erasure processing of a sector to be erased, it is not possible to apply an erasure stress that is as strong as the step-up voltage used in normal erasure processing, however, it is possible to apply an erasure stress weaker than that. Though not complete, an erasure procedure is performed for the other sectors to be erased, and this makes it possible to reduce the time for performing normal erasure processing for the other sectors later.
In a third aspect of the present invention, when performing erasure processing for a sector to be erased while at the same time performing pre-erasure processing for other sectors to be erased, according to the present invention described above, an over erasure verification is performed for other sectors to be erased, and over erased sectors have been detected, the pre-erasure processing is not performed anymore for the other sectors in which an over erasure is detected.
Since the pre-erasure processing is performed at the same time as the erasure processing of a sector to be erased, there is a possibility that cells of other sectors to be erased are over erased. When that happens, the pre-erasure processing is prohibited for other sectors to be erased that have been over erased, and an erasure verification and an over erasure verification are performed in the normal erasure processing which is performed after that. In this way, it is possible to reduce the necessity of unneeded recovery processing, and thus it is possible to shorten the overall erasure process.